An Integrated Multichannel Neural Recording Analog Front-End ASIC with Area-Efficient Driven Right Leg Circuit

Abstract

This paper describes an integrated multichannel neural recording analog front end (AFE) with a novel area-efficient driven right leg (DRL) circuit to improve the system common mode rejection ratio (CMRR). The proposed AFE consists of an AC-coupled low-noise programmable-gain amplifier, an area-efficient DRL block and a 10-bit SAR ADC. Compared to conventional DRL circuit, the proposed capacitor-less DRL design consumes 90% less chip area with comparable CMRR performance, making it ideal for multichannel biomedical recording applications. The AFE circuit has been designed in a standard 0.18-µm CMOS process. Post-layout simulation results show that the AFE provides two gain settings of 54dB/60dB while consuming 1 µA per channel under a supply voltage of 1 V. The input-referred noise of the CCIA amplifier integrated from 1 Hz to 10k Hz is only 4 µVrms and the system CMRR is 110 dB.