Centralized Signal Processing Zero-Forcing Capable Massive MIMO SDR Hardware Using Multi Gigabit Transceivers

Abstract

Massive MIMO (M-MIMO) base station hardware implementation suffers from the problem that massive amounts of sample streams are required to interface with the high number of RF transceivers in the system. Especially, a software defined radio (SDR) system which follows a centralized signal processing (CSP) approach, the CSP field programmable gate array (FPGA) device needs to handle huge amounts of digital I/O data sample streams. This problem can be naturally solved by using the FPGA's integrated multi gigabit wireline transceiver (MGT) circuits, where each MGT offers digital serial data bit streams on a single (differential) transmission line at data rates nowadays ranging up to several tens of Gbit/s. The paper will discuss the advantages of a CSP M-MIMO base station architecture and will provide implementation details on the MGT link design for such a system. Furthermore a custom MGT protocol will be presented which is especially suited for this architecture. All the critical parts in the system are experimentally evaluated with real world hardware and measurement results are provided. Finally it will be shown that in principle such a CSP architecture can be realized with today technology in terms of interconnect requirements for M-MIMO base stations with thousands of antennas.