Improving the Immunity of SET/MOS Hybrid A/D Converters Using Boltzmann Machine Networks

Abstract

Single-electron-transistor (SET)/MOS hybrid architectures greatly simplify the design of traditional A/D converters, but are quite unreliable due to random background charges. We propose a method of implementing Boltzmann machine networks on hybrid ADCs for the improved immunity against background charges. The self-regulation with Boltzmann machines enables the digital outputs of ADC to converge to a stable state when a simulated annealing process is applied. Simulation results with a 3-bit ADC are provided to show the effectiveness of the proposed structure. A possible structure for the higher resolution of ADCs is also presented.