Ultra-Low Standby Power and Static Noise-Immune Standard Ternary Inverter Based on Nanoscale Ternary CMOS Technology

Sunhae Shin1, E-San Jang2, Jeong JaeWon3, Kyung Rok Kim3

  • 1Ulsan National Institute of Science and Technology (UNIST)
  • 2Ulsan National Institute of Science and Technology
  • 3UNIST

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Award Sessions

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10:30 - 12:00 | Wed 26 Jul | Grand Ballroom | WeAPPL

Award Session I

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Abstract

We demonstrate ternary CMOS (T-CMOS)-based standard ternary inverter (STI) for compact and power-scalable multi-valued logic (MVL) circuits. The distinguished mechanism of VG-independent junction band-to-band tunneling (BTBT) for ternary logic has been successfully obtained by CMOS process with a few pA/m level which enables STI operation with ultra-low static power consumption of 7.7 pW/um. Through the STI performance investigation with various T-CMOS structures by using TCAD simulation, advanced nanoscale bulk tri-gate (TG) ternary FinFET (T-FinFET) shows highly noise-immune STI operation with a larger static noise margin (SNM) of 94% to the ideal SNM (230mV) than 86% of bulk planar T-CMOS and 75% of SOI T-CMOS technology.

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